1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a metal oxide semiconductor field-effect transistor (MOSFET) electrostatic discharge (ESD) protection device for preventing a current such as electrostatic surge from flowing into a semiconductor integrated circuit device.
2. Description of the Related Art
Conventionally, semiconductor integrated circuit devices having ESD protection devices provided thereon have been developed. The ESD protection device is provided to prevent a current such as electrostatic surge from flowing into the semiconductor integrated circuit device. Some MOSFET ESD protection devices among the above ESD protection devices are designed to enhance the ESD discharging ability by forming silicide unformed portions (non-silicide regions) in drain regions and source regions (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-339444). That is, since a current is not concentrated in the silicide portion in a diffusion layer in the portion formed as the non-silicide region, the breakdown voltage of the device acting as the ESD protection device is enhanced.
In the ESD protection device, a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate is formed in the non-silicide region in some cases. However, if this method is applied to a transistor for low power source voltage (or low voltage which is hereinafter referred to as LV) used as the ESD protection device, the junction depth of the diffusion layer is reduced and junction leakage may occur in the non-silicide region. In the above document, it is disclosed that the resistance of the non-silicide region is adjusted by using a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate of the LV transistor in the non-silicide region of a transistor for high power source voltage (or high voltage which is hereinafter referred to as HV) used as the ESD protection device.
However, in the above document, it is not disclosed that a countermeasure against junction leakage is taken by forming a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate of the HV transistor in the non-silicide region of the LV transistor.